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DATA SHEET
CX74038: 2.6 GHz/800 MHz Dual Fractional-N/lnteger-N Frequency Synthesizer
Applications
* Multi-slot GSM/DCS * PCS/W-CDMA * Portable communication systems * Dual-mode cellular telephone systems * Spread spectrum receivers * Wireless LAN systems * Wireless routers and WLL systems * SATCOM receivers
Description
The Skyworks CX74038 is a complete, low-power 2.6 GHz/800 MHz dual frequency synthesizer. The device provides both Radio Frequency (RF) channels and Intermediate Frequency (IF) channels. Fractional-N operation offers low phase noise, fast settling time, and low spurious tones for RF channels. A standard integer-N division is used for IF channels. The three-wire serial interface provides programmable control of the frequency synthesizer to support dual-conversion transceivers. The 20-pin Thin Shrink Small Outline Package (TSSOP) device package and pin configuration are shown in Figure 1. A functional block diagram of the CX74038 is shown in Figure 2.
Features
* Maximum operating frequency: 2.6 GHz * Maximum IF synthesizer frequency: 800 MHz * Supply voltage as low as 2.6 V * Fast frequency settling time with fractional-N operation * Internal fractional spur reduction * Programmable charge pump currents * Digital lock detector * Power saving at lower frequency * TSSOP (20-pin, 6.5 x 4.4 x 1.0 mm) package
VDD1_RF VDD2_RF CPO_RF GND RFIN RFINB GND FREF GND LD_TP
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD1_IF VDD2_IF CPO_IF GND IFIN IFINB GND LE DAT CLK
C1452
Figure 1. CX74038 Pinout - 20-Pin TSSOP (Top View)
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DATA SHEET * CX74038
GND
VDD2_RF
VDD1_RF
GND
CPO_RF
GND
R1
SP1
SC1
FREF
R1 Divider
P/FD 1
Charge Pump 1 N1 PS
N1 Divider
P/P+1 Prescaler
RFIN RFINB
LD_TP
MUX (LD/TEST)
FN ME
Modulator Q/Q+1 Prescaler IFIN IFINB LE CLK DAT
LD
N2 Divider
N2 R2 Divider P/FD 2 Charge Pump 2
Serial-to Parallel Interface
R2
SP2
SC2
C1451
VDD2_IF
VDD1_IF
GND
CPO_IF
GND
Figure 2. CX74038 Frequency Synthesizer Block Diagram
Technical Description
The CX74038 is a fractional-N frequency synthesizer using a modulation technique. The fractional-N implementation provides low in-band noise by having a low division ratio and fast frequency settling time. In addition, the CX74038 provides arbitrarily fine frequency resolution with digital words, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the RF transceiver. Modulator Fractional spurs are the primary limitation of conventional fractional-N synthesizers. The CX74038 technique improves the synthesizer performance by randomizing the spurs using internal dithering. Serial Interface The serial interface is a versatile three-wire interface consisting of three pins: the serial clock (CLK), serial input (DAT), and Latch Enable (LE). This interface enables the CX74038 to operate in a system where one or multiple masters and slaves are present. For more information, refer to the Synthesizer Register Programming section of this document.
As shown in Figure 3, LE is set low before the rising edge of the first clock (CLK) pulse and is held low until after the last (22nd) clock pulse, at which time LE is set high. The data word is transferred to the correct device register when LE is high (there are four internal registers selected by the D1 and D0 bits of the 22-bit data/address word. See Figure 4). If the LE signal does not go high, the data does not get transferred to the register. Between each 22-bit data/address word transfer, LE must be pulsed to make the transfer to the specific device register. Data/address transfer is MSB first. LE must not go high when CLK is high; otherwise, the data word is not transferred to the register. LE must only go high after CLK has gone low. After the transfer of the last 22-bit data/address word, the LE signal can be left in a high state. It does not have to be returned to a low state unless another data/address word transfer is required. It is not necessary to write all four data/address words to the synthesizer to make a change in programming. For example, if a change to the Lock Detect (LD) pin operation is desired, only word 00 has to be changed.
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DATA SHEET * CX74038
DAT
CLK
LE tDSU tDHD tCKH tCKL tCLE tLEW
C1457
tLEC
Figure 3. CX74038 Serial Data Input Timing Diagram (MSB First)
MSB
D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 LD EN R1 DIVIDER FN PS SC1 D4 D3 SC2 SP2 SP1 D2 D1 0 1 0 1
LSB
D0 0 IF N2 DIVIDER ME N1 DIVIDER 0 1 RF 1
C1456
R2 DIVIDER
Figure 4. CX74038 Serial Data Word Format
Registers The CX74038 includes four 22-bit registers that can be programmed independently in any order. Bits D0 and D1 represent the register addresses. For more information on registers, addresses, and format, refer to the Synthesizer Register Programming section of this document. A dithering disable function is accessible via word 00, data bits 21 and 20. When the RF synthesizer is programmed for fractional divide values, these bits should be programmed to 1 0 (dithering enable). However, when the RF synthesizer is programmed to output a frequency which is a whole integer multiple of the comparison frequency, the synthesizer should be programmed for dithering disabled (bits set to 11). This improves the phase noise when operating on integer-N boundaries. These data bits must be programmed after power-up, otherwise erroneous device operation may occur. Refer to the Synthesizer Register Programming section of this document for bit definitions. Voltage Controlled Oscillator (VCO) Prescalers The VCO prescalers, P/P+1 and Q/Q+1, provide low noise signal conditioning of the VCO signals. They translate from an off-chip, single-ended or differential signal to an on-chip differential signal. By changing the PS bit, the RF synthesizer has the option to use either the 8/9 or the 16/17 prescaler depending on the desired
operational frequency. The maximum frequency is 2.6 GHz for the 16/17 prescaler and 1.4 GHz for the 8/9 prescaler. The IF synthesizer has a fixed 16/17 prescaler with a maximum frequency of 800 MHz. RF and IF Dividers The CX74038 provides programmable dividers that control the prescaler and supply the divided VCO signals to the charge pump phase detectors. Programmable ratios on the RF fractional-N synthesizer ranging from 256 to 212 are possible with the 16/17 prescaler, and from 64 to 211 with the 8/9 prescaler. The IF integer-N synthesizer has a programmable divide ratio ranging from 256 to 217. Reference Frequency Dividers The reference signal can be divided by a ratio of 1 to 7 for the RF reference divider (R1) and from 1 to 8192 for the IF reference divider (R2). The input frequency for the reference signal can be as high as 50 MHz. Phase Detectors and Charge Pumps The CX74038 uses a separate charge pump phase detector for each synthesizer. The IF and RF Phase/Frequency Detector (PFD)
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DATA SHEET * CX74038
can have a programmable charge pump current from 0.4 mA to 1.6 mA and 120 A to 480 A, respectively. For optimum performance, the divided reference frequency presented at the phase detector input must not exceed 9 MHz using the RF 16/17 prescaler synthesizer mode, 15 MHz using the RF 8/9 prescaler, or 2 MHz for the IF synthesizer mode. The comparison frequency is also limited by the desired frequency divided by the minimum divide ratio. The charge-pump can be programmed to high impedance (Hi-Z) state for open-loop VCO modulation use. Lock Detection The output of the IF/RF dividers (R1, N1, R2, N2) and lock detectors for both synthesizers can be multiplexed to the LD pin. When programmed for lock detection, the CX74038 provides an active low output to indicate the out-of-lock condition. When locked, the LD pin is high. Power Down The CX74038 supports a number of power-down modes through the serial interface. Both IF and RF synthesizer blocks can be powered down, powered up individually, or both powered up using the EN bits (see the Synthesizer Register Programming section of this document). The CX74038 is enabled at power up by default. Synthesizer Register Programming IF Integer-N Synthesizer. The N2 17-bit divider ratio is calculated using the following equation:
IF = N2 F REF -----------R2
FN sets the fractional-N modulo up to 256 modulo, as calculated by:
1 111FN = D 9 -- + D 8 ---- + D 7 ---- + ... + D 2 ---2 3 8 2 2 2 2
where:
Dn represents the bit locations within the register field.
The fractional modulo can be extended up to 221 using the modulo extender (ME), if required, as shown by the following equation:
1 1 1 1 ME = D21 ---- + D20 ------- + D19 ------- + ... + D9 ------9 10 11 21 2 2 2 2
Because the way the modulator is implemented in the CX74038, the number 3.5 must be added to the division number to obtain the final division ratio. If the integer field of the N divider shows a non-integer number, the desired frequency or the division fraction portion needs to be adjusted. Sample calculations for two fractional-N applications are shown in Figure 5.
Electrical and Mechanical Specifications
Signal pin assignments and functional pin descriptions are specified in Table 1. The absolute maximum ratings of the CX74038 are provided in Table 2. The recommended operating conditions are specified in Table 3 and electrical characteristics are provided in Table 4. Table 5 provides the register descriptions. Package dimensions for the CX74038 are shown in Figure 6 and tape and reel dimensions for the 20-pin TSSOP package are shown in Figure 7.
Electrostatic Discharge Information
The CX74038 is an electrostatic sensitive device. Observe precautions when handling.
As with all integer-N synthesizers, the minimum step size is related to the divided reference frequency, FREF. RF Fractional-N Synthesizer. The N1 divider ratio is calculated using the following equation:
F REF RF = -----------R1 N1 Total
where:
N1Total = N1 + 3.5 + FN + ME
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DATA SHEET * CX74038
Case 1: To achieve a desired FVCO_RF frequency of 2440.2 MHz using a crystal frequency of 24 MHz with operation of the synthesizer in RF mode using the 16/17 prescaler (PS = 1). R1 is set to divide by 3 to achieve a comparison frequency of 8 MHz, since the maximum internal reference frequency is 9 MHz. Divide the operating frequency by the internal reference frequency to determine the value of NTotal:
NTotal
= 2440.2 MHz 8 MHz = 305.025
Subtract 3.5 from NTotal and remove the fractional portion of the result to determine N1:
305.025 - 3.5 = 301.525 N1 = 301 (decimal) Fractional portion = 0.525 (decimal) N1 = 000100101101 (binary) D21 -----------D10 Register Address 112 Multiply the fractional portion of N1 by 256 and remove the fractional portion of the result to determine FN: 0.525 x 256 = 134.4 FN = 134 (decimal) FN = 10000110 (binary) D9 -------D2 Register Address 112
Divide FN by 256 to determine the actual fractional portion:
134 = 0.5234375 256 Subtract this result from the fractional portion of N1: 0.525 - 0.5234375 = 0.0015625 Multiply this result by 2097152 (the 21-bit modulator value 221) and remove the fractional portion to determine the ME: 0.0015625 x 2097152 = 3276.8 ME = 3276 (decimal) ME = 0110011001100 (binary) D21 --------------D9 Register Address 012
In this example, N1 is greater than 256, the minimum divide ratio for the 16/17 prescaler.
C1454
Figure 5. Fractional-N Applications: Sample Calculation (1 of 2)
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DATA SHEET * CX74038
Case 2: To achieve a desired FVCO_RF frequency of 1400 MHz using a crystal frequency of 13 MHz with operation of the synthesizer in RF mode using the 8/9 prescaler (PS = 0). The crystal frequency does not need to be divided further, since the maximum comparison frequency is 15 MHz. Divide the operating frequency by the internal reference frequency to determine the value of NTotal:
NTotal
= 1400 MHz 13 MHz =107.6923076
Subtract 3.5 from NTotal and remove the fractional portion of the result to determine N1:
107.6923076 - 3.5 = 104.1923076 N1 = 104 (decimal) Fractional portion = 0.1923076 (decimal) N1 = 000001101000 (binary) D21 ------------D10 Register Address 112 Multiply the fractional portion of N1 by 256 and remove the fractional portion of the result to determine FN: 0.1923076 x 256 = 49.230746 FN = 49 (decimal) FN = 00110001 (binary) D9 -------D2 Register Address 112
Divide FN by 256 to determine the actual fractional portion:
49 = 0.1914962 256 Subtract this result from the fractional portion of N1: 0.1923076 - 0.1914062 = 0.0009014 Multiply this result by 2097152 (the 21-bit modulator value 221) and remove the fractional portion to determine the ME: 0.0009014 x 2097152 = 1890.3728 ME = 1890 (decimal) ME = 0011101100010 (binary) D21 --------------D9 Register Address 012
In this example, N1 is greater than 64, the minimum divide ratio for the 8/9 prescaler.
C1455
Figure 5. Fractional-N Applications: Sample Calculation (2 of 2)
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DATA SHEET * CX74038
Table 1. CX74038 Signal Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 Pin Name VDD1_RF VDD2_RF CPO_RF GND RFIN RFINB GND FREF GND LD_TP I/O -- -- O -- I I -- I -- O Description Power supply for RF digital circuits Power supply for RF analog circuits RF charge pump output Ground RF prescaler input RF prescaler complementary input Ground Reference divider input Ground Multiplexed output from lock detectors and dividers Pin # 11 12 13 14 15 16 17 18 19 20 Pin Name CLK DAT LE GND IFINB IFIN GND CPO_IF VDD2_IF VDD1_IF I/O I I I -- I I -- O -- -- Description Serial interface clock input Serial interface data input Serial interface Latch Enable input Ground IF prescaler complementary input IF prescaler input Ground IF charge pump output Power supply for IF analog circuits Power supply for IF digital circuits
Table 2. Absolute Maximum Ratings
Parameter Power supply with GND = 0 V Voltage on any pin Storage temperature Minimum -0.3 GND -65 +150 Maximum +3.6 Units V V C
Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal values.
Table 3. Recommended Operating Conditions
Parameter Power supply Operating junction temperature Operating ambient temperature Min 2.6 -40 -40 Max 3.6 +100 +85 Units V C C
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DATA SHEET * CX74038
Table 4. Electrical Characteristics (VDD = 2.7 V, TA = 25 C, unless otherwise noted)
Parameter Supply voltage Supply current Symbol Test Conditions RF/IF RF @2.5 GHz IF RF/IF @2.5 GHz-RF Standby RF (PS = 1) RF (PS = 0) IF (@ -40 C to +85 C) Reference input frequency Phase detector frequency RF (PS = 1) RF (PS = 0) IF (@ -40 C to +85 C) Prescaler input sensitivity RF IF (@ -40 C to +85 C) Prescaler input impedance Reference oscillator sensitivity In-band phase noise @ 10 kHz offset (Note 1) RF @ 2.5 GHz IF @ 480 MHz (@ -40 C to +85 C) Charge pump output current RF, VCP = VDD/2 -15% -15% -15% -15% -15% -15% -15% -15% 120 240 360 480 0.4 0.8 1.2 1.6 0.2 0.5 -10 -5 -10 0.7 VDD 0.3 VDD tCKH tCKL tDSU tDHD tLEW tCLE tLEC 20 20 5 5 20 5 5 +10 +8 +20 +15% +15% +15% +15% +15% +15% +15% +15% A A A A mA mA mA mA nA nA % % % V V ns ns ns ns ns ns ns RF @ 2.5 GHz IF @ 480 MHz 0.3 -85 -82 30 - j25 200 - j190 VDD Vp-p dBc/Hz dBc/Hz -15 -15 +6 +6 dBm dBm 50 9 15 2 MHz MHz MHz MHz 0.1 0.1 1 Minimum 2.6 Typical 2.7 6.5 1.9 8.2 10 2.6 1.4 800 Maximum 3.6 Units V mA mA mA A GHz GHz MHz
Operating input frequency
IF, VCP = VDD/2
Charge pump leakage current Charge pump sink vs. source mismatch Charge pump current vs. voltage/temperature High level digital I/O voltage Low level digital I/O voltage Serial clock high time Serial clock low time Data set-up time to clock rising-edge Data hold time to clock rising-edge LE pulse width Clock falling-edge to LE rising edge LE falling-edge to clock rising-edge
0.5 < VCP < VDD - 0.5 0.3 < VCP < VDD - 0.3 VCP = VDD/2 0.5 < VCP < VDD - 0.5 0.3 < VCP < VDD - 0.3
Note 1: RF output frequency = 2.5 GHz, comparison frequency = 8 MHz, loop bandwidth = 35 kHz, and charge pump current = 480 mA. IF output frequency = 480 MHz, comparison frequency = 200 kHz, loop bandwidth = 10 kHz, and charge pump current = 1.6 mA.
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DATA SHEET * CX74038
Table 5. CX74038 Register Descriptions (1 of 2)
Symbol Register Word Address 00 Address bits [1:0] SC2 IF synthesizer charge-pump output current [3:2] 00 Bits [3:2] select the IF synthesizer charge pump output current: bit 3 0 0 1 1 LD Test mode [6:4] bit 2 0 1 0 1 Selects 0.4 mA charge pump output current Selects 0.8 mA charge pump output current Selects 1.2 mA charge pump output current Selects 1.6 mA charge pump output current Function Description
Bits [6:4] set the test mode: bit 6 0 0 0 0 1 1 1 1 bit 5 bit 4 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 multiplexes Ndiv output of IF SX to LD output multiplexes Rdiv output of IF SX to LD output multiplexes lock detect output of IF SX to LD output multiplexes ANDed lock detect of both SX to LD output multiplexes Ndiv output of RF SX to LD output multiplexes Rdiv output of RF SX to LD output multiplexes lock detect output of RF SX to LD output Hi-Zs the charge-pump output of RF SX
R2
IF synthesizer reference divider [19:7] RF synthesizer fractional-N mode selection [21:20] (Note 1)
Bits [19:7] set the IF synthesizer 13-bit reference divider ratio Bits [21:20] set the RF synthesizer fractional-N mode: bit 21 bit 20 0 0 1 1 0 1 0 1 Reserved Reserved Fractional-N mode with dithering Fractional-N mode without dithering
Register Word Address 01 Address bits [1:0] SP1 RF synthesizer phase detector output polarity [2] 01 Bit [2] sets the polarity of the RF synthesizer phase detector output: 0 Sets phase detector output for negative VCO gain 1 Sets phase detector output for positive VCO gain Bits [4:3] set the RF synthesizer charge pump output current: bit 4 0 0 1 1 PS RF synthesizer prescaler selection [5] bit 3 0 1 0 1 Selects 120 A charge pump output current Selects 240 A charge pump output current Selects 360 A charge pump output current Selects 480 A charge pump output current
SC1
RF synthesizer charge-pump output current [4:3]
Bit [5] selects the RF synthesizer prescaler: 0 Select 8/9 prescaler 1 Select 16/17 prescaler
R1 ME
RF synthesizer reference divider [8:6] RF synthesizer modulo extender [21:9]
Bits [8:6] set the RF synthesizer's 3-bit reference divider ratio Bits [21:9] extend the RF synthesizer's fractional modulo up to 2,097,152 (optional)
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DATA SHEET * CX74038
Table 5. CX74038 Register Descriptions (2 of 2)
Symbol Register Word Address 10 Address bits [1:0] SP2 IF synthesizer phase detector output polarity [2] 10 Bit [2] sets the IF synthesizer phase detector output: 0 Sets phase detector output for negative VCO gain 1 Sets phase detector output for positive VCO gain Bits [4:3] enable the RF and/or IF synthesizers: bit 4 0 0 1 1 N2 IF synthesizer main divider [21:5] bit 3 0 1 0 1 Enables both RF SX and IF SX Enables only RF SX Enables only IF SX Sets power-down mode for both RF/IF SX Function Description
EN
Enable mode [4:3]
Bits [21:5] set the IF synthesizer 17-bit main divider ratio
Register Word Address 11 Address bits [1:0] FN N1 RF synthesizer fractional-N division [9:2] RF synthesizer main divider [21:10] 11 Bits [9:2] set the RF synthesizer's fractional-N program up to 256 modulo Bits [21:10] set the RF synthesizer's 12-bit main divider ratio with a 16/17 prescaler, or an 11-bit main divider ratio with 8/9 prescaler
Note 1: These bits must be programmed after power is applied to the device. Failure to do so may result in erroneous device operation.
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DATA SHEET * CX74038
0.65
Pin #1 indicator
6.5 0.10
Top View
4.40 0.10
Bottom View
1.00 +0.05/-0.20 6.50 0.10
1.00 Ref 4.40 0.10 0.24 +0.06/-0.05
1.20 max
0.10 0.05
End View
All measurements are in millimeters
Side View
C003
Figure 6. CX74038 20-Pin TSSOP Package Dimensions
8.00 0.10
4.00 0.10
1.50 0.10 2.00 0.05
1.75 0.10
B
Pin #1 indicator
5.50 0.05
A
A
B
1.50 0.25 4.00 0.292 0.013 1.20 8o Max 7o Max
6.75 0.10
1.70 0.10
7.05 0.10
A
Notes: 1. Carrier tape material: black conductive polystyrene 2. Cover tape material: transparent conductive PSA 3. Cover tape size: 9.3 mm width 5. All measurements are in millimeters
B
C879
Figure 7. CX74038 20-Pin TSSOP Tape and Reel Dimensions
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12.00 +0.30/-0.10
11
DATA SHEET * CX74038
Ordering Information
Model Name CX74038 2.6 GHz/800 MHz Frequency Synthesizer CX74038-12 Manufacturing Part Number Evaluation Kit Part Number PH00-D222
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